1. Field of the Invention
The present invention relates to an arrangement by which a circuit provided with an asynchronous bus can be adapted to peripheral interface circuits that require a synchronous bus.
2. Description of the Related Art
Many digital processors have an asynchronous bus which is controlled by two timing control signals. An asynchronous bus may cause difficulties in applications that are strict as far as timing is concerned. The libraries of some producers of Application Specific Integrated Circuits (from hereafter "ASIC circuits") also contain synchronous memories only, or using such a memory instead of an asynchronous memory is otherwise feasible. In order to adapt a synchronous memory to an asynchronous bus, interface logic is required.
In many digital processors, such as the AT&T.RTM. signal processor DSP1610, the bus is controlled by two timing control signals. In the figures, they are presented as signals ENA' and RWN. State 0 of the signal ENA' (Enable) indicates that the processor carries out either a read or a write transaction. State 0 of the signal RWN (Read/Write-Not) indicates that the processor is writing to peripheral circuits, and state 1 of the same signal indicates that the processor is reading from the peripheral circuits. If ENA' is "1", the state of the signal RWN' is of no importance.
Formerly, digital processors have been coupled to ASIC circuits by applying both of the control signals ENA' and RWN to peripheral circuits. This results in certain drawbacks. First of all, some circuits only have one line to which a timing control signal can be coupled. In addition, the fact that the transitions of the signals ENA' and RWN have not necessarily been synchronized to the system clock (CKO) may cause problems in applications that are critical as far as timing is concerned. Furthermore, some ASIC circuit suppliers only have synchronous memories to offer, which means that it is not possible to employ all existing peripheral interface circuits on an asynchronous bus. In addition, an environment requiring two control signals for timing is rather poorly, or not at all, supported by development tools. Test generation is also facilitated if timing takes place with one control signal.